In synchronous serial-port communication, a transmitter device sends a clock signal and a data signal simultaneously, and a receiver device samples data according to the clock signal.
In actual engineering applications, due to factors such as the length of the cable from the transmitter device to the receiver device and intra-board wiring, delay of the data signal may be inconsistent with delay of the clock signal. However, in data sampling, requirements of setup time and hold time must be satisfied simultaneously, and if any requirement is not satisfied, the data obtained by sampling may be incorrect. Setup time refers to a minimum period during which the data signal must keep stable before the sampling edge, and hold time refers to a minimum period during which the data signal must keep stable after the sampling edge. Therefore, the following case may exist at the receiver device: The rising edge of the clock signal must be used as the sampling edge for sampling data, or the falling edge of the clock signal must be used as the sampling edge for sampling data.
Generally, a receiver of the receiver device uses a fixed clock edge to sample the data signal. Therefore, a selecting signal needs to be provided for a selector according to the selected sampling edge, so that the selector selects the original clock signal or the clock signal inverted by an inverter (also called a NOT gate) as a sampling clock signal and provides the sampling clock signal for the receiver. Specifically, if the clock edge for sampling data by the receiver of the receiver device is the same as the selected sampling edge, the original clock signal is selected as the sampling clock signal; and if the clock edge for sampling data by the receiver of the receiver device is different from the selected sampling edge, the clock signal inverted by the inverter is selected as the sampling clock signal.
In synchronous serial-port communication in the prior art, a selecting signal is input to the selector by manually configuring the sampling edge, so that the selector selects a sampling clock signal. Generally, a configuration personnel does not know which clock edge should be configured for sampling, and can determine the sampling edge only by attempts. For example, first the clock edge for sampling data by the receiver is configured manually as the rising edge, and a corresponding selecting signal is input to the selector, for example, 1, so that the selector selects a sampling clock signal for the receiver according to the selecting signal; then packet loss and bit error rate of the device are observed manually for a period; and if no packet loss and bit error occurs, the configured sampling edge does not need to be adjusted; while if packet loss or bit error is found, the clock edge for sampling data by the receiver is configured manually as the falling edge, and a corresponding selecting signal is input to the selector, so that the selector selects a sampling clock signal for the receiver according to the selecting signal. As a result, the system maintainability is poor and the cost of operation and maintenance is high.